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Design of low power full adder using multilayer perceptron to minimize energy delay product of computational logic circuits

by Pakkiraiah, C | Satyanarayana, R. V. S.

Edition: Vol.15(2), AprSource: IUP journal of electrical and electronics engineeringPublisher: Hyderabad IUP Publications 2022Online access: Click here Availability: Items available for reference: School of Engineering & Technology (1).

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Performance of NOMA in 5G mobile wireless networks

by Rachana, M | Satyanarayana, R. V. S.

Edition: Vol.14(2), MaySource: IUP Journal of telecommunications Publisher: Hydrabad IUP Publications 2022Online access: Click here Availability: Items available for reference: School of Engineering & Technology (1).

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